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105

SAM7S Series [DATASHEET]

6175M–ATARM–26-Oct-12

19. Embedded Flash Controller (EFC)

19.1

Overview

The Embedded Flash Controller (EFC ) is a part of the Memory Controller and ensures the interface of the Flash

block with the 32-bit internal bus. It increases performance in Thumb Mode for Code Fetch with its system of 32-bit

buffers. It also manages the programming, erasing, locking and unlocking sequences using a full set of commands.

The SAM7S512 is equipped with two EFCs, EFC0 and EFC1. EFC1 does not feature the Security bit and GPNVM

bit. The Security and GPNVM bits embedded only on EFC0 apply to the two blocks in the SAM7S512.

19.2

Functional Description

19.2.1

Embedded Flash Organization

The Embedded Flash interfaces directly to the 32-bit internal bus. It is composed of several interfaces:

One memory plane organized in several pages of the same size

Two 32-bit read buffers used for code read optimization (see “Read Operations” on page 107).

One write buffer that manages page programming. The write buffer size is equal to the page size. This buffer is

write-only and accessible all along the 1 MByte address space, so that each word can be written to its final

address (see “Write Operations” on page 109).

Several lock bits used to protect write and erase operations on lock regions. A lock region is composed of

several consecutive pages, and each lock region has its associated lock bit.

Several general-purpose NVM bits. Each bit controls a specific feature in the device. Refer to the product

definition section to get the GPNVM assignment.

The Embedded Flash size, the page size and the lock region organization are described in the product definition

section.

Table 19-1.

Product Specific Lock and General-purpose NVM Bits

SAM7S512

SAM7S256

SAM7S128

SAM7S64

SAM7S321

SAM7S32

SAM7S161

SAM7S16

Denomination

Number of GPNVM bits

Number of Lock Bits

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